¡¡PA61¤Ç¸¡º÷¤·¤Æ¤¤¤¿¤é¡¢Ë¿µðÂç·Ç¼¨ÈĤÇPA61¤¬ÃÙ¤¤¤È½ñ¤¹þ¤ó¤Ç¤¤¤ë¿Í¤¬µï¤¿¡£ÃΤé¤ì¤Æ¤¤¤Ê¤¤»ö¤À¤¬¡¢¤³¤Î¥Þ¥¶¡¼¤Ï¥Ð¡¼¥¸¥ç¥óG°Ê¹ß(ºÇ½ª¤ÏI)¤ÎBIOS¤Ç¤Ï¶ËÅ٤˥á¥â¥ê®ÅÙ¤¬Äã²¼¤¹¤ë¡£F¤«¤éG¤ÇÊѹ¹¤¬¤¢¤Ã¤¿¤Î¤Ï¥ì¥¸¥¹¥¿50H¤È51H¤À¤±¡£¤·¤«¤·50H¤ÏDFIÀßÄê¤Î3DH¤ÏÃÙ¤¯D1H[11010001]¤¬Îɤ¤¡£51H¤âD8H¤Ç¤Ï¤Ê¤¯D9H[11011001]¤ÎÊý¤¬Â®¤¤¡£
¡¡¤½¤³¤òÊѹ¹¤¹¤ì¤Ð¥Ð¡¼¥¸¥ç¥óF°Ê¾å¤Ë¤Ï¤Ê¤ë¡£¤Ê¤ªBIOSÀßÄê¤Ë¤è¤Ã¤Æ¤Ï¸µÃͤ¬°ã¤Ã¤Æ¤¤¤ë¾ì¹ç¤¬¤¢¤ë¡£¤³¤ÎÊѹ¹¤Î°ÕÌ£¤ÏÁ°µ»ö¤òÆɤá¤ÐÇö¡¹µ¤¤Å¤¯¤À¤í¤¦¡£Ê̤˵¤¤Å¤«¤Ê¤¯¤Æ¤â¤¤¤¤¤±¤É(¡°¡°
¡á50H-3DH[00111101]¡á
50h:Request Phase Control (00h)
7 CPU Hardwired IOQ (In Order Queue) Size
0 1-Level
1 4-Level
6 Read-Around-Write
0 Disable(default)
1 Enable
5 Reserved always reads 0
4 Defer Retry When HLOCK Active
0 Disable(default)
1 Enable
3-1 Reserved always reads 0
0 CPU / PCI Master Read DRAM Timing
0 Start DRAM read after snoop complete(default)
1 Start DRAM read before snoop complete
¡á51H-D8H[11011000]¡á
51h:Response Phase Control (00h)
7 CPU Read DRAM 0ws for B2B Read Transactions
0 Disable(default)
1 Enable
¡¡¤³¤Î¥Ó¥Ã¥È¤¬ÀßÄꤵ¤ì¤Ê¤¤¤È¡¢¥ê¡¼¥É¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Î´Ö¤Ë¤Ï¾¯¤Ê¤¯¤È¤â1TÍ·µÙ»þ´Ö¤¬¤¢¤ë¤À¤í¤¦¡£
6 CPU Write DRAM 0ws for B2B Write Transactions
0 Disable(default)
1 Enable
¡¡¤³¤Î¥Ó¥Ã¥È¤¬ÀßÄꤵ¤ì¤Ê¤¤¤È¡¢¥é¥¤¥È¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Î´Ö¤Ë¤Ï¾¯¤Ê¤¯¤È¤â1TÍ·µÙ»þ´Ö¤¬¤¢¤ë¤À¤í¤¦¡£
5 Reserved always reads 0
4 Fast Response (HIT/HITM sample 1T earlier)
0 Disable(default)
1 Enable
3 Non-Posted IOW
0 Disable(default)
1 Enable
2-1 Reserved always reads 0
0 Concurrent PCI Master / Host Operation
0 Disable(default)
1 Enable -
¡¡¥Ç¥£¥»¡¼¥Ö¥ë¤À¤ÈPCI¥ª¥Ú¥ì¡¼¥·¥ç¥ó¤Î´ÖÃæ CPU bus¤¬Àêͤµ¤ì¤ë(BPRI¥¢¥µ¡¼¥È)¡£¥¤¥Í¡¼¥Ö¥ë¤À¤ÈADS#¥¢¥µ¡¼¥È¤ÎÁ°¤ËÍ׵ᤵ¤ì¤ë¤À¤±¡£
¡ú693A¤½¤Î¾HostBridgeÀßÄê
¡¡*¤¬Êѹ¹¤·¤¿¥¢¥É¥ì¥¹¡£³Æ´Ä¶²¼¤ÇºÇŬÃͤǤ¢¤ëÊݾڤÏ̵¤¤¡£
50:3D[00111101]¢ªD1[11010001]*
51:D8[11011000]¢ªD9[11011001]*
52:C8[11001000]¢ªC8[11001000]
53:00[00000000]¢ª00[00000000]
54:00[00000000]¢ª00[00000000]
55:00[00000000]¢ª00[00000000]
56:10[00010000]¢ª10[00010000]
57:10[00010000]¢ª10[00010000]
58:08[00001000]¢ª08[00001000]
59:00[00000000]¢ª00[00000000]
5A:00[00000000]¢ª00[00000000]
5B:00[00000000]¢ª00[00000000]
5C:08[00001000]¢ª08[00001000]
5D:10[00010000]¢ª10[00010000]
5E:10[00010000]¢ª10[00010000]
5F:10[00010000]¢ª10[00010000]
60:0C[00001100]¢ª0C[00001100]
61:0A[00001010]¢ª0A[00001010]
62:00[00000000]¢ª00[00000000]
63:20[00100000]¢ª20[00100000]
64:D4[11010100]¢ª12[00010010]*
65:D4[11010100]¢ª12[00010010]*
66:D4[11010100]¢ª12[00010010]*
67:D4[11010100]¢ª12[00010010]*
68:21[00100001]¢ªE1[11100001]*
69:20[00100000]¢ª20[00100000]
6A:65[01100101]¢ª65[01100101]
6B:0F[00001111]¢ª2D[00101101]*
6C:40[01000000]¢ª48[01001000]*
6D:21[00100001]¢ª21[00100001]
6E:00[00000000]¢ª00[00000000]
6F:00[00000000]¢ª00[00000000]
¡¡ÀßÄ꤬ÌÌÅݤʤé¤ÐBIOS¼«ÂΤò½ñ¤´¹¤¨¤Æ¤âÎɤ¤¡£¤Ê¤ªPA61¤Ï²ÏƸB¥¹¥Æ¥Ã¥×(683)¤Þ¤Ç¤·¤«Âбþ¤·¤Æ¤¤¤Ê¤¤¡£Windows9x(Ãí)¤È²ÏƸC¥¹¥Æ¥Ã¥×°Ê¹ß¤ÎÁȤ߹ç¤ï¤»¤À¤ÈÆ°¤«¤Ê¤¤¾ì¹ç¤¬¤¢¤ë¤Î¤Ç¡¢¥Þ¥¶¡¼¤ä¤½¤Î¾¥Ñ¡¼¥Ä¤òµÕº¨¤ß¤·¤Ê¤¤¤è¤¦¤Ë¡£¤½¤Î¾ì¹ç¤Ï¥Þ¥¤¥¯¥í¥³¡¼¥É¤â¥¢¥Ã¥×¥Ç¡¼¥È¤·¤Ê¤¯¤Æ¤ÏÀµ¾ïÆ°ºî¤·¤Ê¤¤¡£¤ä¤êÊý¤Ï°ÊÁ°½ñ¤¤¤¿¤è¤Ê¡£
¡¡¤½¤³¤òÊѹ¹¤¹¤ì¤Ð¥Ð¡¼¥¸¥ç¥óF°Ê¾å¤Ë¤Ï¤Ê¤ë¡£¤Ê¤ªBIOSÀßÄê¤Ë¤è¤Ã¤Æ¤Ï¸µÃͤ¬°ã¤Ã¤Æ¤¤¤ë¾ì¹ç¤¬¤¢¤ë¡£¤³¤ÎÊѹ¹¤Î°ÕÌ£¤ÏÁ°µ»ö¤òÆɤá¤ÐÇö¡¹µ¤¤Å¤¯¤À¤í¤¦¡£Ê̤˵¤¤Å¤«¤Ê¤¯¤Æ¤â¤¤¤¤¤±¤É(¡°¡°
¡á50H-3DH[00111101]¡á
50h:Request Phase Control (00h)
7 CPU Hardwired IOQ (In Order Queue) Size
0 1-Level
1 4-Level
6 Read-Around-Write
0 Disable(default)
1 Enable
5 Reserved always reads 0
4 Defer Retry When HLOCK Active
0 Disable(default)
1 Enable
3-1 Reserved always reads 0
0 CPU / PCI Master Read DRAM Timing
0 Start DRAM read after snoop complete(default)
1 Start DRAM read before snoop complete
¡á51H-D8H[11011000]¡á
51h:Response Phase Control (00h)
7 CPU Read DRAM 0ws for B2B Read Transactions
0 Disable(default)
1 Enable
¡¡¤³¤Î¥Ó¥Ã¥È¤¬ÀßÄꤵ¤ì¤Ê¤¤¤È¡¢¥ê¡¼¥É¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Î´Ö¤Ë¤Ï¾¯¤Ê¤¯¤È¤â1TÍ·µÙ»þ´Ö¤¬¤¢¤ë¤À¤í¤¦¡£
6 CPU Write DRAM 0ws for B2B Write Transactions
0 Disable(default)
1 Enable
¡¡¤³¤Î¥Ó¥Ã¥È¤¬ÀßÄꤵ¤ì¤Ê¤¤¤È¡¢¥é¥¤¥È¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Î´Ö¤Ë¤Ï¾¯¤Ê¤¯¤È¤â1TÍ·µÙ»þ´Ö¤¬¤¢¤ë¤À¤í¤¦¡£
5 Reserved always reads 0
4 Fast Response (HIT/HITM sample 1T earlier)
0 Disable(default)
1 Enable
3 Non-Posted IOW
0 Disable(default)
1 Enable
2-1 Reserved always reads 0
0 Concurrent PCI Master / Host Operation
0 Disable(default)
1 Enable -
¡¡¥Ç¥£¥»¡¼¥Ö¥ë¤À¤ÈPCI¥ª¥Ú¥ì¡¼¥·¥ç¥ó¤Î´ÖÃæ CPU bus¤¬Àêͤµ¤ì¤ë(BPRI¥¢¥µ¡¼¥È)¡£¥¤¥Í¡¼¥Ö¥ë¤À¤ÈADS#¥¢¥µ¡¼¥È¤ÎÁ°¤ËÍ׵ᤵ¤ì¤ë¤À¤±¡£
¡ú693A¤½¤Î¾HostBridgeÀßÄê
¡¡*¤¬Êѹ¹¤·¤¿¥¢¥É¥ì¥¹¡£³Æ´Ä¶²¼¤ÇºÇŬÃͤǤ¢¤ëÊݾڤÏ̵¤¤¡£
50:3D[00111101]¢ªD1[11010001]*
51:D8[11011000]¢ªD9[11011001]*
52:C8[11001000]¢ªC8[11001000]
53:00[00000000]¢ª00[00000000]
54:00[00000000]¢ª00[00000000]
55:00[00000000]¢ª00[00000000]
56:10[00010000]¢ª10[00010000]
57:10[00010000]¢ª10[00010000]
58:08[00001000]¢ª08[00001000]
59:00[00000000]¢ª00[00000000]
5A:00[00000000]¢ª00[00000000]
5B:00[00000000]¢ª00[00000000]
5C:08[00001000]¢ª08[00001000]
5D:10[00010000]¢ª10[00010000]
5E:10[00010000]¢ª10[00010000]
5F:10[00010000]¢ª10[00010000]
60:0C[00001100]¢ª0C[00001100]
61:0A[00001010]¢ª0A[00001010]
62:00[00000000]¢ª00[00000000]
63:20[00100000]¢ª20[00100000]
64:D4[11010100]¢ª12[00010010]*
65:D4[11010100]¢ª12[00010010]*
66:D4[11010100]¢ª12[00010010]*
67:D4[11010100]¢ª12[00010010]*
68:21[00100001]¢ªE1[11100001]*
69:20[00100000]¢ª20[00100000]
6A:65[01100101]¢ª65[01100101]
6B:0F[00001111]¢ª2D[00101101]*
6C:40[01000000]¢ª48[01001000]*
6D:21[00100001]¢ª21[00100001]
6E:00[00000000]¢ª00[00000000]
6F:00[00000000]¢ª00[00000000]
¡¡ÀßÄ꤬ÌÌÅݤʤé¤ÐBIOS¼«ÂΤò½ñ¤´¹¤¨¤Æ¤âÎɤ¤¡£¤Ê¤ªPA61¤Ï²ÏƸB¥¹¥Æ¥Ã¥×(683)¤Þ¤Ç¤·¤«Âбþ¤·¤Æ¤¤¤Ê¤¤¡£Windows9x(Ãí)¤È²ÏƸC¥¹¥Æ¥Ã¥×°Ê¹ß¤ÎÁȤ߹ç¤ï¤»¤À¤ÈÆ°¤«¤Ê¤¤¾ì¹ç¤¬¤¢¤ë¤Î¤Ç¡¢¥Þ¥¶¡¼¤ä¤½¤Î¾¥Ñ¡¼¥Ä¤òµÕº¨¤ß¤·¤Ê¤¤¤è¤¦¤Ë¡£¤½¤Î¾ì¹ç¤Ï¥Þ¥¤¥¯¥í¥³¡¼¥É¤â¥¢¥Ã¥×¥Ç¡¼¥È¤·¤Ê¤¯¤Æ¤ÏÀµ¾ïÆ°ºî¤·¤Ê¤¤¡£¤ä¤êÊý¤Ï°ÊÁ°½ñ¤¤¤¿¤è¤Ê¡£
Ãí¡§ºÇ¤â¿·¤·¤¤ME¤Ç¤¹¤é683¤Þ¤Ç¤·¤«Âбþ¤·¤Æ¤¤¤Ê¤¤¡£686°Ê¹ß¤Ïɬ¤ºBIOS¤ÇÂбþ¤¹¤ëɬÍפ¬¤¢¤ë¡£P6Á´Âбþ¤Ï2000SP2°Ê¹ß¡£